The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to a process that increases the etch control on the thin gate oxidation near the edges of a poly-silicon or amorphous silicon gate stack.
One important stage in the manufacture of a semiconductor device involves photolithography and etching. In photolithography, a wafer substrate is coated with a light-sensitive material called photo-resist. The wafer is then exposed to a pattern of light. The pattern is created by passing the light through a mask plate prior to etch. The mask plate defines the desired features to be printed on the substrate. After exposure, the resist-coated wafer substrate is developed. The desired features as defined on the mask are retained on the photoresist-coated substrate. Unexposed areas of resist are washed away. The wafer is then subjected to etching. Depending upon the production process, the etching may either be a wet etch in which liquid chemicals are used to remove wafer material or a dry etch in which wafer material is subjected to a radio frequency (RF) induced plasma.
In many modern sub-micron processes, the gate electrode is comprised of a composite of layers of materials xe2x80x9cstackedxe2x80x9d on top of one another, hence the name, xe2x80x9cgate stack.xe2x80x9d A commonly used gate stack is amorphous silicon (xcex1-Si) or poly silicon (poly-Si) on top of a thin gate oxide. The xcex1-Si or poly-Si is typically doped with N-type carriers for NMOS or with P-type carriers for PMOS to obtain asymmetry threshold voltage between N-channel and P-channel devices for a CMOS device. As IC dimensions are reduced in size, thinner gate oxide is required to maintain an acceptable level of gate capacitance.
Different doping types, doses, and activation levels of the xcex1-Si or poly-Si have significant effects on the xcex1-Si or poly-Si etch rate as well as the etch profile. N-doped xcex1-Si or poly-Si usually etches faster than P-doped xcex1-Si or poly-Si in a plasma etch process. Under the N-type material, thin gate oxide, may be exposed to the plasma and removed when etching the P-type material. A localized breakthrough, xe2x80x9cmicrotrenching,xe2x80x9d of the thin gate oxidation in the bottom of the xcex1-Si or poly-Si etch features can result. Micro-trenches are small trenches formed in the bottom of the xcex1-Si features mostly adjacent to the sidewall, and the subsequent rapid etching of the underlying silicon.
With a relatively thin gate oxide, microtrenching is problematic, especially in N-doped areas. In a plasma etch process, a gate etch profile is also very sensitive to the doping of xcex1-Si or poly-Si. In addition, the doping profiles between N-doped and P-doped xcex1-Si or poly-Si may be different especially for dense xcex1-Si or poly-Si lines. Consequently, there may also be unacceptable critical dimension (CD) variation among gate stacks in dense and sparse areas. Such CD variation in the gate significantly affects the performance of the manufactured devices.
Accordingly, a need exists for a gate etch process that is substantially free of micro-trenching and achieves consistent etch profiles in N/P-type doped gate stacks, as well as good critical dimension control as the process technology approaches fractional microns.
The present invention is exemplified in a number of implementations, two of which are summarized below. During the forming of gate stack structures of a transistor, the invention minimizes microtrenching of the thin gate oxide adjacent to the silicon gate structures. Additionally, the invention provides for gate etch profiles which are nearly vertical and consistent across the wafer. In accordance with a first embodiment of the invention, a method for etching unmasked areas of a gate stack having an anti reflective coating (ARC) formed on a doped amorphous-silicon layer on a silicon oxide on a substrate, comprises first placing the substrate into an etch chamber. Then the ARC layer is etched with a breakthrough etch until the layer of amorphous silicon is exposed. Next, a bulk etch etches the amorphous-silicon layer until about 40% of the amorphous silicon remains. Following the bulk etch, the process etches the remaining amorphous-silicon layer with a high selectivity etch until the silicon oxide is exposed. The remaining amorphous-silicon layer is etched with a very high-selectivity over-etch until all of the amorphous silicon residues are cleared. An additional feature of this embodiment is that poly-silicon may be substituted for the amorphous silicon used in the silicon layer of the gate stack. Also, the ARC layer may be silicon oxy-nitride or one of a number of materials having similar properties.
The above process achieves the desired gate stack profiles by using, in part, a low bias power and a low Cl2/HBr flow ratio. Desirable gate stack profiles are in the range of about 85xc2x0 to 90xc2x0 with respect to the substrate. The low Cl2/HBr ratio enhances the etch selectivity. Undesirable removal of gate oxide is substantially minimized as the amorphous or poly silicon is etched.
In another embodiment according to the present invention, a method for selectively etching a gate stack having a silicon layer covering a thin oxide layer which covers a substrate, the silicon layer having a hard mask layer thereon comprises etching through the hard mask layer of the gate stack, with a first process gas having a fluorine-based chemistry, until the silicon layer is exposed. With a second process gas, including a mixture of HBr, Cl2, and CF4, the silicon layer of the gate stack is etched. Then the gate stack is etched with a third process gas including a mixture of HBr, Cl2, and 80% Hexe2x80x94O2 until the thin oxide is exposed. The gate stack is over etched with a fourth process gas including a mixture of HBr, 80% Hexe2x80x94O2, and He. An additional feature of this embodiment is that silicon layer may be formed from amorhous silicon or poly silicon. Also, the hard mask layer may be silicon oxy-nitride or one of a number of materials having similar properties.
Again, desirable gate stack profiles are in the range of about 85xc2x0 to 90xc2x0 with respect to the substrate are attained. The undesirable removal of the gate oxide is substantially minimized during etch of the amorphous or poly silicon.